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发表于 2016-3-22 17:19:35
楼主
我接了一个最佳分辨率为1366X768的VGA显示器，firefly驱动读取EDID信息是正确的，也正确地去配置分辨率1366x768@60Hz了。实际效果看起来整个屏幕位置偏移了不少，从显示器内置的工具看真实分辨率为1024x768@69Hz。
分析了开机log，关键信息摘录如下:
<4>[ 1.731042] vga-ddc: max mode 1366x768@59[pixclock-85506 KHZ]
......
<4>[ 1.731256] rk_fb_switch_screen lcdc_id 0 type 1 enable 1
<4>[ 1.731266] fb0 win id 1 state 1
<4>[ 1.731273] post stx 0 sty 0 xsize 1366 ysize 768
<6>[ 1.731276] regulator-dummy: disabling
<4>[ 1.731285] dev_drv->overscan.left = 100,dev_drv->overscan.right = 100,dev_drv->overscan.top = 100,dev_drv->overscan.bottom = 100
<6>[ 1.731331] rk3288-lcdc lcdc0: lcdc0: dclk:99000000>>fps:69
这段打印在rk3288_lcdc.c的rk3288_lcdc_set_dclk()中，可以看到设置下去的clk和读取的clk不一致，pixclock应该分配85506KHz的，结果分配了99000KHz。
[mw_shl_code=c,false]static int rk3288_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
{
#ifdef CONFIG_RK_FPGA
return 0;
#endif
int ret,fps;
struct lcdc_device *lcdc_dev =
container_of(dev_drv, struct lcdc_device, driver);
struct rk_screen *screen = dev_drv->cur_screen;
ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
if (ret)
dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
lcdc_dev->pixclock =
div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
screen->ft = 1000 / fps;
dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
return 0;
}
[/mw_shl_code]
再查看RK提供的资料，也提到存在DCLK分配不到想要的频率的可能性。有没有高手解决了这个问题？
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